Field of the Invention
The disclosure relates generally to duty cycle calibration circuits, and more particularly it relates to duty cycle calibration circuits utilizing a synchronous clock signal generated by a signal-generating circuit to calibrate the duty cycle.
Description of the Related Art
Integrated circuit (IC) devices include circuits or logic elements that may be used to perform any of a variety of functions. Oftentimes, these devices are used in a larger system to perform complex functions. As an example, in a relatively complex system (e.g., a computer system, a communication system, etc.), multiple IC devices may communicate with one another to perform system functions.
Generally, such devices require a clock signal to operate. The clock signal synchronizes communication between two different devices. Circuits that are designed to operate with a clock signal (commonly referred to as synchronous circuits) are generally activated at the rising or falling edge of the clock signal. Certain interfaces, however, allow data transfer on both the rising and falling edges of the clock signal to achieve higher data transfer rates.
Generally, a clock signal is presented as a square wave and the duty cycle may refer to the percentage of clock period that the clock signal remains at a logic high (logic 1) or a logic low level (logic 0). As such, a clock signal that spends half its clock period at logic 1 and the other half at logic 0 is said to have a balanced duty cycle or a 50% duty cycle. In high data rate applications, where both the rising and falling edges of the clock signal are used to sample data, it may be important for the clock signal to have a 50% duty cycle. Once the duty cycle is unbalanced or not 50%, it results in some unnecessary problems in the system. Therefore, devices and methods of generating a 50% duty cycle are urgently required to solve this problem.